1. Field of the Invention
The invention relates in general to comparators, and more specifically, to digital comparators formed of MOS gates.
2. Description of the Prior Art
Digital word comparators are required in various digital control, computer and logic applications. A typical application is the decoding or recognition of a word consisting of N-bits. For example, in digital communications it is necessary for a remote receiving point to recognize when it is uniquely addressed by a digital word of N-bits. A 16-bit address word would have 2.sup.16 or 65,536 different combinations, and a given location must recognize a specific one of these combinations. Thus, the addressed location requires a variable-fixed word comparator. It is also often necessary to compare two variable words and to determine when they are equal.
The advantages of using the metal-oxide-semiconductor (MOS) field effect transistor in integrated digital logic arrays makes it attractive to provide digital word comparators with MOS devices.
A typical fixed-variable word comparator using integrated circuit gates requires sixteen inverters or NOT gates for obtaining the complement of each bit, four four-input NAND gates, and a four-input NOR gate. The fixed word to be recognized is implemented by connecting the 16 inputs of the NAND gates to the bits of the words, or the complements of the bits, as required to provide all logic ones to the NAND gate inputs when the variable word is equal to the specific fixed word. The outputs of the four NAND gates are connected to the inputs of the NOR gate. Thus, when the variable word is equal to the fixed word, the outputs of all four NAND gates will be at the logic zero level, and the output of the NOR gate will be a logic one, indicating equality. This arrangement requires 72 field effect transistors, and a total of six integrated circuit (IC) packages.
It would be desirable to be able to provide a digital comparator which requires fewer gates and fewer IC packages. The reduced package count will reduce the cost of the comparator when selecting standard available IC packages, and the lower gate count will reduce the chip cost of a "custom" integrated circuit.